Micromechanical and microoptomechanical structures with backside metalization

ABSTRACT

The present invention provides a micromechanical or microoptomechanical structure produced by a process comprising defining the structure in a single-crystal silicon layer separated by an insulator layer from a substrate layer; selectively etching the single crystal silicon layer; depositing and etching a polysilicon layer on the insulator layer, with remaining polysilicon forming mechanical elements of the structure; metalizing a backside of the structure; and releasing the formed structure.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is a divisional of U.S. patent application Ser.No. 09/724,515, filed Nov. 27, 2000, and claims priority therefrom under35 U.S.C. § 120. The priority application is currently pending.

FIELD OF THE INVENTION

[0002] Micromechanical and microoptomechanical structures fabricated onsilicon-on-insulator (SOI) wafers are described. More particularlymicromechanical and mircooptomechanical components created by chemicallyand mechanically modifying SOI wafers and metalizing a backside of thecomponents are described.

BACKGROUND

[0003] Inherent thin film properties of materials limit many surfacemicromachining processes. For example, variability of materialsproperties in polysilicon thin films (such as Young's modulus andPoisson's ratio, residual stress, and stress gradients) can prohibitmanufacture of desired microstructures. This is particularly apparent inmicrooptical components such as mirrors, lenses, and diffractiongratings, which must be very flat for high-optical performance, andnormally have to be made in the single crystal silicon layer. Sinceconventional surface micromachining requires that all components be madein polysilicon layers, optical performance can be limited.

[0004] The leading commercial microelectromechanical (MEMS) processingtechnologies are (1) bulk micromachining of single crystal silicon, and(2) surface micromachining of polycrystalline silicon. Each of theseprocessing technologies has associated benefits and barriers. Bulkmicromachining of single crystal silicon, an excellent material withwell-controlled electrical and mechanical properties in its pure state,has historically utilized wet anisotropic wet etching to form mechanicalelements. In this process, the etch rate is dependent on thecrystallographic planes that are exposed to the etch solution, so thatmechanical elements are formed that are aligned to the rate limitingcrystallographic planes. For silicon these planes are the (1,1,1)crystal planes. The alignment of mechanical features to thecrystallographic planes leads to limitations in the geometries that canbe generated using this technique. Typical geometries include v-groovetrenches and inverted pyramidal structures in (1,0,0) oriented siliconwafers, where the trenches and inverted pyramids are bound by (1,1,1)crystallographic planes. Geometries that include convex corners are notallowed unless additional measures are taken to protect etching of thecrystal planes that make up the corners. The etch rate also varies withdopant concentration, so that the etch rate can be modified by theincorporation of dopant atoms, which substitute for silicon atoms in thecrystal lattice. A boron dopant concentration on the order of 5×10¹⁹/cm³is sufficient to completely stop etching, so that mechanical elementsbounded by other crystal planes can be generated by using dopant “etchstop” techniques. However, dopant concentrations of this magnitude aresufficient to modify the desirable electrical and mechanical propertiesof the pure single crystal silicon material, leading to device designand manufacturability constraints. Recent advances in Deep Reactive IonEtching (DRIE) (see, e.g., J. K. Bhardwaj and H. Ashraf, “Advancedsilicon etching using high density plasmas”, Micromachining andMicrofabrication Process Technology, Oct. 23-24, 1995, Austin, Tex.,SPIE Proceedings Vol. 2639, pg. 224) which utilize sidewall passivationand ion beam directionality to achieve etch anisotropy, have relaxed thein-plane geometric design constraints, but still require etch stoptechniques to control the depth of the etch into the wafer, andadditional processing steps are required to undercut a structure torelease it from the substrate.

[0005] In contrast to bulk micromachining, surface micromachining ofpolycrystalline silicon utilizes chemical vapor deposition (CVD) andreactive ion etching (RIE) patterning techniques to form mechanicalelements from stacked layers of thin films (see, e.g., R. T. Howe,“Surface micromachining for microsensors and microactuators”, J. Vac.Sci. Technol. B6, (1988) 1809). Typically CVD polysilicon is used toform the mechanical elements, CVD nitride is used to form electricalinsulators, and CVD oxide is used as a sacrificial layer. Removal of theoxide by wet or dry etching releases the polysilicon thin filmstructures. The advantage of the surface micromachining process is theability to make complex structures in the direction normal to the wafersurface by stacking releasable polysilicon layers (see, e.g., K. S. J.Pister, M. W. Judy, S. R. Burgett, and R. S. Fearing, “Microfabricatedhinges”, Sensors and Actuators A33, (1992) 249 and L. Y. Lin, S. S. Lee,K. S. J. Pister, and M. C. Wu, “Micromachined three-dimensionalmicro-optics for free-space optical system”, IEEE Photon. Technol. Lett.6, (1994) 1445) and complete geometric design freedom in the plane ofthe wafer since the device layers are patterned using isotropic RIEetching techniques. An additional advantage of surface micromachining isthat it utilizes thin film materials such as polysilicon, oxide,nitride, and aluminum, that are commonly used in microelectronic devicefabrication, albeit with different materials properties that areoptimized for mechanical rather than electrical performance. Thiscommonality in materials allows for increased integration ofmicroelectronic and micromechanical components into the same fabricationprocess, as demonstrated in Analog Devices' integrated accelerometer,and in SSI Technologies' integrated pressure sensor.

[0006] While surface micromachining relaxes many of the limitationsinherent in bulk micromachining of single crystal silicon, itnonetheless has its own limitations in thin film properties. The maximumfilm thickness that can be deposited from CVD techniques are limited toseveral microns, so that thicker structures must be built up fromsequential depositions. Thicker device layers are required for dynamicoptical elements where dynamic deformations can impact opticalperformance, and for optical elements which require additional thin filmcoatings that can cause stress-induced curvature. The thin filmmechanical properties, such as Young's modulus and Poisson's ratio, aredependent on the processing parameters and the thermal history of thefabrication process, and can typically vary by as much as 10% from runto run. This is an important limitation for robust manufacturabilitywhere these thin film mechanical properties can be a critical parameterfor device performance.

[0007] An additional limitation of conventional surface micromachiningis that holes through the mechanical elements must be included in thedesign to allow the etchants used to release the mechanical elements toreach the sacrificial layers. While this is not an important limitationfor optical elements such as Fresnel lenses and diffraction grating thatinclude holes in their design, it is an important limitation for opticalelements such as mirrors where holes are a detriment to opticalperformance. Flatness and reflectivity are also important optical designcriteria that can be impacted by conventional surface micromachiningprocesses. Thin film stresses and stress gradients, typical ofpolysilicon thin films, can lead to warping of optical surfaces. Inaddition the surface of as-deposited polysilicon thin films is notpolished, and thus requires post-processing Chemical MechanicalPolishing (CMP) techniques to obtain an optical quality surface finish.

SUMMARY OF THE INVENTION

[0008] The present invention provides a micromechanical ormicrooptomechanical structure produced by a process comprising definingthe structure in a single-crystal silicon layer separated by aninsulator layer from a substrate layer; selectively etching the singlecrystal silicon layer; depositing and etching a polysilicon layer on theinsulator layer, with remaining polysilicon forming mechanical elementsof the structure; metalizing a backside of the structure; and releasingthe formed structure.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009]FIG. 1 illustrates in perspective view a MEMS device havingvarious optical and mechanical elements formed in accordance with theprocess of the present invention; and

[0010]FIG. 2 is a cross-sectional view of a silicon-on-insulator (SOI)wafer in which MEMS and MOEMS devices can be created according to thepresent invention;

[0011] FIGS. 3-18 show an embodiment of process steps used to form aMEMS device such as those illustrated in FIG. 1.

DETAILED DESCRIPTION OF THE INVENTION

[0012] Described below is an embodiment of the present inventive processand device. The embodiment illustrates only one of the several ways thepresent invention may be implemented. Although the embodiment isdescribed in the context of a moving mirror on a silicon-on-insulator(SOI) chip, it could easily be used for other components. In thedescription that follows, like numerals represent like elements or stepsin all figures. For example, if the numeral 10 is used in a figure torefer to a specific element or step, the numeral 10 appearing in anyother figure refers to the same element.

[0013]FIG. 1 illustrates some of the very complex microelectromechanical(MEMS) and microoptoelectromechanical (MOEMS) devices that can beconstructed on a silicon wafer using the embodiment of the presentinvention. The device 200 includes movable optical elements constructedfrom single crystal silicon overlaying an insulator such as adiffraction grating 202, a grating 204, and a Fresnel lens 206. Activeelectronic elements can also be defined in the single crystal siliconlayer, including flip chip bonded light producing laser diodes 201,light detecting photodiodes 203, or conventional CMOS logic circuitry205. Bulk modifications required for packaging or mounting of thesubstrate are also possible, such as illustrated by etched cavity 208,and added polysilicon layers can be used for mechanical elements such ashinges 209.

[0014]FIG. 2 shows an embodiment of a silicon-on-insulator (SOI) wafer10 suitable for use in the embodiment of the process described herein.The SOI wafer 10 includes a thin single crystal silicon device waferlayer 12, and a substrate layer 14. The substrate layer 14 is preferablypolysilicon. Between these two layers 12 and 14 there is a buried oxide(BOX) layer 16 that integrally bonds the device layer 12 and thesubstrate layer 14. This buried oxide layer 16 can also be used as anetch stop in wet and dry etching procedures to form a thin membrane. Inaddition, there is a back oxide layer 18 on the back side of thesubstrate layer 14, which is used to control etch down to the interfacebetween the device layer 12 and substrate layer 14 from the backside.Preferably, the wafer is circular with a diameter of 100 mm±0.5 mm and athickness of 525±25 microns. The overall thickness of the wafer is madeup of 1±0.5 microns of backside oxide 20, 1±0.05 microns of buried oxide(BOX), and 5±0.5 microns of single crystal silicon. The remainder of thethickness is made up of the substrate.

[0015] Before beginning processing, the wafer is inspected to verifythat it meets the manufacturer's specifications. If it meets thespecifications, the wafer is inscribed with a lot and wafer number,cleaned, and 2000 Å of thermal oxide 20 are grown on top of the singlecrystal silicon layer 12 to act an etch stop in a later polysilicon etchand to prevent doping of the SCS by a later polysilicon glass (PSG)layer.

[0016] FIGS. 3-18, considered in conjunction with the following detailedsteps 1-84, illustrate an embodiment of a process used on the wafer ofFIG. 2 to produce the grating 204 of the microstructure 200 illustratedin FIG. 1. The process illustrated below can also be used for othertypes of components; it all depends on what is patterned into the wafer.The patterning of the structures on the wafer is done using standardphotolithography techniques well known in the art, which typicallycomprise depositing layers of the correct materials on the wafer,applying a photoresist on the wafer, exposing the photoresist in areasto be added (light mask) or removed (dark mask) and then performing theappropriate etch. Step # Process Comments 1. Thermal oxidation 1000° C.,2000 Å 2. Photolithography a) bake 110 degree C., 15 min Mask #1:Substrate_Contact b) HMDS, 5.OK, 30 sec c) AZ1813, 4.OK, 30 SEC, 1.3 umd) softbake 90 C., 30 min e) expose, 5.0 mW/cm², 12 sec f) develop MF319, 1.1 min g) rinse, DI water, 4 min h) spin dry i) hardbake 110degree C., 30 min 3. Oxide etch RIE: CF₄, target etch rate: 2500 Å/min4. SCS etch RIE: HBr, Cl₂, target etch rate: 5000 Å/min 5. Oxide etchRIE: CF₄, target etch rate: 2500 Å/min 6. Strip photoresist Hot PRS2000,20 min rinse DI water, 5 min spin, dry 7. Photolithography a) bake 110degree C., 15 min Mask #2: SCS_Dimple b) HMDS, 5.OK, 30 sec c) AZ1813,4.OK, 30 SEC, 1.3 um d) softbake 90 C., 30 min e) expose, 5.0 mW/cm², 12sec f) develop MF 319, 1.1 min g) rinse, DI water, 4 min h) spin dry i)hardbake 110 degree C., 30 min 8. Oxide etch RIE: CF₄, target etch rate:2500 Å/min 9. SCS etch RIE: HBr, Cl₂, target etch rate: 5000 Å/min 10.Oxide etch RIE: CF₄, target etch rate: 2500 Å/min 11. Strip photoresistHot PRS2000, 20 min rinse DI water, 5 min spin, dry 12. Polysilicondeposition LPCVD, 3 μm 13. Polysilicon etch RIE: HBr, Cl₂, target etchrate: 5000 Å/min 14. Oxide etch RIE: CF₄, target etch rate: 2500 Å/min15. Photolithography a) bake 110 degree C., 15 min Mask #3: SCS_Gratingb) HMDS, 5.OK, 30 sec c) AZ1813, 4.OK, 30 SEC, 1.3 um d) softbake 90 C.,30 min e) expose, 5.0 mW/cm², 12 sec f) develop MF 319, 1.1 min g)rinse, DI water, 4 min h) spin dry i) hardbake 110 degree C., 30 min 16.SCS etch RIE: HBr, Cl₂, target etch rate: 5000 Å/min 17. Stripphotoresist Hot PRS2000, 20 min rinse DI water, 5 min spin, dry 18.Photolithography a) bake 110 degree C., 15 min Mask #4: SCS_Hole b)HMDS, 5.OK, 30 sec c) AZ1813, 4.OK, 30 SEC, 1.3 um d) softbake 90 C., 30min e) expose, 5.0 mW/cm², 12 sec f) develop MF 319, 1.1 min g) rinse,DI water, 4 min h) spin dry i) hardbake 110 degree C., 30 min 19. SCSetch RIE: HBr, Cl₂, target etch rate: 5000 Å/min 20. Strip photoresistHot PRS2000, 20 min rinse DI water, 5 min spin, dry 21. TEOS depositionLPCVD, 8 μm 22. Densification 800° C., 1 hour 23. CMP Leave 2 +/− 0.2 μm24. Photolithography a) bake 110 degree C., 15 min Mask #5: Anchor_SCSb) HMDS, 5.OK, 30 sec c) AZ1813, 4.OK, 30 SEC, 1.3 um d) softbake 90 C.,30 min e) expose, 5.0 mW/cm², 12 sec f) develop MF 319, 1.1 min g)rinse, DI water, 4 min h) spin dry i) hardbake 110 degree C., 30 min 25.Oxide etch RIE: CF₄, target etch rate: 2500 Å/min 26. Strip photoresistHot PRS2000, 20 min rinse DI water, 5 min spin, dry 27. Nitridedeposition LPCVD, 6000 Å 28. Photolithography a) bake 110 degree C., 15min Mask #6: Nitride_Struct b) HMDS, 5.OK, 30 sec c) AZ1813, 4.OK, 30SEC, 1.3 um d) softbake 90 C., 30 min e) expose, 5.0 mW/cm², 12 sec f)develop MF 319, 1.1 min g) rinse, DI water, 4 min h) spin dry i)hardbake 110 degree C., 30 min 29. Nitride etch RIE: CF₄, target etchrate: 2500 Å/min 30. Strip photoresist Hot PRS2000, 20 min rinse DIwater, 5 min spin, dry 31. Polysilicon deposition LPCVD, 5000 Å 32.Photolithography a) bake 110 degree C., 15 min Mask #7: Poly0_Struct b)HMDS, 5.OK, 30 sec c) AZ1813, 4.OK, 30 SEC, 1.3 um d) softbake 90 C., 30min e) expose, 5.0 mW/cm², 12 sec f) develop MF 319, 1.1 min g) rinse,DI water, 4 min h) spin dry i) hardbake 110 degree C., 30 min 33.Backside polysilicon strip RIE: SF₆, O₂ 34. Polysilicon etch RIE: HBr,Cl₂, target etch rate: 5000 Å/min 35. Strip photoresist Hot PRS2000, 20min rinse DI water, 5 min spin, dry 36. PSG deposition PECVD, 2 μm 37.Photolithography a) bake 110 degree C., 15 min Mask #8: Poly1_Dimple b)HMDS, 5.OK, 30 sec c) AZ1813, 4.OK, 30 SEC, 1.3 um d) softbake 90 C., 30min e) expose, 5.0 mW/cm², 12 sec f) develop MF 319, 1.1 min g) rinse,DI water, 4 min h) spin dry i) hardbake 110 degree C., 30 min 38. Oxideetch RIE: CF₄, target etch rate: 2500 Å/min 39. Strip photoresist HotPRS2000, 20 min rinse DI water, 5 min spin, dry 40. Photolithography a)bake 110 degree C., 15 min Mask #9: PSG1_Hole b) HMDS, 5.OK, 30 sec c)AZ1813, 4.OK, 30 SEC, 1.3 um d) softbake 90 C., 30 min e) expose, 5.0mW/cm², 12 sec f) develop MF 319, 1.1 min g) rinse, DI water, 4 min h)spin dry i) hardbake 110 degree C., 30 min 41. Oxide etch RIE: CF₄,target etch rate: 2500 Å/min 42. Strip photoresist Hot PRS2000, 20 minrinse DI water, 5 min spin, dry 43. Polysilicon deposition LPCVD, 2 μm44. PSG deposition PECVD, 2000 Å 45. Anneal 1000° C., 1 hour 46.Backside polysilicon strip RIE: SF₆, O₂ 47. Photolithography a) bake 110degree C., 15 min Mask #10: Poly1_Struct b) HMDS, 5.OK, 30 sec c)AZ1813, 4.OK, 30 SEC, 1.3 um d) softbake 90 C., 30 min e) expose, 5.0mW/cm², 12 sec f) develop MF 319, 1.1 min g) rinse, DI water, 4 min h)spin dry i) hardbake 110 degree C., 30 min 48. Oxide etch RIE: CF₄,target etch rate: 2500 Å/min 49. Polysilicon etch RIE: HBr, Cl₂, targetetch rate: 5000 Å/min 50. Strip photoresist Hot PRS2000, 20 min rinse DIwater, 5 min spin, dry 51. Oxide etch RIE: CF₄, target etch rate: 2500Å/min 52. Oxide deposition PECVD, 7500 Å 53. Photolithography a) bake110 degree C., 15 min Mask #11: PSG2_Hole b) HMDS, 5.OK, 30 sec c)AZ1813, 4.OK, 30 SEC, 1.3 um d) softbake 90 C., 30 min e) expose, 5.0mW/cm², 12 sec f) develop MF 319, 1.1 min g) rinse, DI water, 4 min h)spin dry i) hardbake 110 degree C., 30 min 54. Oxide etch RIE: CF₄,target etch rate: 2500 Å/min 55. Strip photoresist Hot PRS2000, 20 minrinse DI water, 5 min spin, dry 56. Photolithography a) bake 110 degreeC., 15 min Mask #12: PSG2_PSG2_Hole b) HMDS, 5.OK, 30 sec c) AZ1813,4.OK, 30 SEC, 1.3 um d) softbake 90 C., 30 min e) expose, 5.0 mW/cm², 12sec f) develop MF 319, 1.1 min g) rinse, DI water, 4 min h) spin dry i)hardbake 110 degree C., 30 min 57. Oxide etch RIE: CF₄, target etchrate: 2500 Å/min 58. Strip photoresist Hot PRS2000, 20 min rinse DIwater, 5 min spin, dry 59. Polysilicon deposition LPCVD, 1.5 μm 60.Oxide deposition PECVD, 2000 Å 61. Anneal 1000° C., 1 hour 62.Photolithography a) bake 110 degree C., 15 min Mask #13: Poly2_Struct b)HMDS, 5.OK, 30 sec c) AZ1813, 4.OK, 30 SEC, 1.3 um d) softbake 90 C., 30min e) expose, 5.0 mW/cm², 12 sec f) develop MF 319, 1.1 min g) rinse,DI water, 4 min h) spin dry i) hardbake 110 degree C., 30 min 63.Backside polysilicon strip RIE: SF₆, O₂ 64. Oxide etch RIE: CF₄, targetetch rate: 2500 Å/min 65. Polysilicon etch RIE: HBr, Cl₂, target etchrate: 5000 Å/min 66. Oxide etch RIE: CF₄, target etch rate: 2500 Å/min67. Strip photoresist Hot PRS2000, 20 min rinse DI water, 5 min spin,dry 68. Oxide etch RIE: CF₄, target etch rate: 2500 Å/min 69.Photolithography a) bake 110 degree C., 15 min Mask #14: SCS_Expose b)HMDS, 5.OK, 30 sec c) AZ1813, 4.OK, 30 SEC, 1.3 um d) softbake 90 C., 30min e) expose, 5.0 mW/cm², 12 sec f) develop MF 319, 1.1 min g) rinse,DI water, 4 min h) spin dry i) hardbake 110 degree C., 30 min 70. Oxideetch HF 71. Photolithography a) bake 110 degree C., 15 min Mask #15:Thick_Metal b) HMDS, 5.OK, 30 sec c) AZ1813, 4.OK, 30 SEC, 1.3 um d)softbake 90 C., 30 min e) expose, 5.0 mW/cm², 12 sec f) develop MF 319,1.1 min g) rinse, DI water, 4 min h) spin dry i) hardbake 110 degree C.,30 min 72. Metal evaporation Cr/Au: 300 Å/5000 Å 73. Lift-off Hot 1112A74. Photolithography a) bake 110 degree C., 15 min Mask #16: Thin_Metalb) HMDS, 5.OK, 30 sec c) AZ1813, 4.OK, 30 SEC, 1.3 um d) softbake 90 C.,30 min e) expose, 5.0 mW/cm², 12 sec f) develop MF 319, 1.1 min g)rinse, DI water, 4 min h) spin dry i) hardbake 110 degree C., 30 min 75.Metal evaporation Cr/Au: 200 Å/300 Å 76. Lift-off Hot 1112A 77.Photolithography a) bake 110 degree C., 15 min Mask #17: Back b) HMDS,5.OK, 30 sec c) AZ1813, 4.OK, 30 SEC, 1.3 um d) softbake 90 C., 30 mine) expose, 5.0 mW/cm², 12 sec f) develop MF 319, 1.1 min g) rinse, DIwater, 4 min h) spin dry i) hardbake 110 degree C., 30 min 78. Nitrideetch RIE: CF₄, target etch rate: 2500 Å/min 79. Oxide etch RIE: CF₄,target etch rate: 2500 Å/min 80. Protect front side Spin-on coat(proprietary) 81. Strip photoresist (backside) Hot PRS2000, 20 min rinseDI water, 5 min spin, dry 82. KOH etch 45%, 65-85° C. 83. Nitride etchRIE: CF₄, target etch rate: 2500 Å/min 84. Oxide etch RIE: CF₄, targetetch rate: 2500 Å/min

[0017]FIG. 3 illustrates the wafer at the conclusion of step 6.Substrate contact holes 22 about 4 microns wide are patterned onto theSCS layer 12 of the wafer. A reactive ion etch (RIE) of the thermaloxide 20 is performed, and the SCS layer 12 is etched through to theburied oxide 16, also using a reactive ion etch. The photoresist used topattern the holes 22 is left on to protect the rest of the oxide 20, andan RIE etch of the exposed buried oxide 16 is performed 1 micron down.This etches the BOX layer 16 away and leaves the substrate layer 14exposed at the bottom of the contact holes 22.

[0018]FIG. 4 illustrates the state of the wafer at the conclusion ofstep 14. SCS dimple holes 24 4 microns wide are patterned onto the SCSlayer 12 and an RIE etch of the thermal oxide 20 is performed, followedby an RIE etch of the SCS layer 12 through to the BOX layer 16. Thephotoresist is left on to protect the rest of the thermal oxide 20 andan RIE etch of the exposed BOX layer 16 is performed until about halfthe thickness of the BOX layer is etched away. The photoresist isremoved and polysilicon 26 is deposited to fill the dimple 24 andsubstrate contact holes 22. In this embodiment, 2.5 microns ofpolysilicon should be enough, since the dimples 24 and substratecontacts 22 are 4 microns wide. The polysilicon 26 is etched with an RIEusing the thermal oxide 20 as an etch stop. This removes the polysilicon26 from everywhere except in the dimple and substrate contact holes,where the level of the polysilicon will be lower than the rest of thewafer, depending on the amount of polysilicon overetch.

[0019]FIG. 5 illustrates the state of the wafer at the conclusion ofstep 17. A pattern in the form of a grating 28 is first applied to theSCS layer 12. The grating 28 must be applied to the wafer at this earlystage of processing. Optimum focusing of the applied mask is neededbecause the line spacing of the grating is of the same order as thewavelength of light, meaning that the resolution must be as good aspossible. To assure optimum focus, the grating 28 must be applied to thewafer when there is little or no topography already built up. Thisensures that there are no problems with depth of focus that would affectthe quality of the resulting grid. In addition, applying the grid whilethere is minimum topography on the wafer ensures that there is noadverse effects from shadows cast by topographical features that arepresent. Once the grating 28 is patterned on the wafer, a quick RIEoxide etch is then performed to remove the thermal oxide 20, followed bya 3 micron RIE etch of the SCS layer 12. The photoresist used to applythe grating 28 is then removed.

[0020] Various types of gratings 28 can be applied to the SCS layer 12;the exact type of grid will depend on the application of the particularmicromechanical or microoptomechanical device. Examples of gratingsinclude a Fresnel pattern useful for reflective optical applications; auniform square grating useful for light frequency division inapplications such as a spectrum analyzer; and a variable pitch gridwhere sets of lines in the grating are spaced in variable increments toachieve better spectral coverage of certain wavelengths and enhanceoptical power. Different gratings may also be used for other opticalpurposes, such as a crystal oscillator which changes resonance based onsurface effects, or for non-optical purposes such as chemical orbiological sensors, where the grating increases the available surfacearea for chemical or biological binding.

[0021]FIG. 6 illustrates the wafer at the conclusion of step 23. The SCSlayer 12 is patterned with full-depth features 30, and a quick RIE etchis performed to remove the thermal oxide 20. A chlorine-based RIE etchis performed all the way through the SCS layer 12, using the BOX layer16 as an etch stop. 0.2 microns of undoped, low pressure chemical vapordeposition (LPCVD) oxide (not shown) are deposited to protect thesidewalls of the full-depth features 30. Six (6) microns ofplanarization oxide (POX) 32 are deposited so that the wafer will beflat after later chemical mechanical polishing (CMP); the planarizationoxide 32 is preferably boron polysilicate glass (BPSG) or thermallyenhanced oxide (TEOS). A timed chemical mechanical polish of the POX 32is performed until 2±0.2 microns of the planarization oxide 32 remain onthe SCS layer 12.

[0022]FIG. 7 illustrates the wafer at conclusion of step 27. A pair ofholes 34 are patterned in the POX layer 32, and an RIE etch is performedto transfer the pattern into the POX 32 and down to the SCS layer. Thephotoresist is removed and a nitride layer 36 with a thickness of 0.6microns is deposited via LPCVD. A second nitride layer 38 is alsodeposited on the back of the wafer for extra selectivity during a laterpotassium hydroxide (KOH) etch.

[0023]FIG. 8 illustrates the wafer at the conclusion of step 31. Theresist on the pattern front side is patterned with nitrite structuresand the pattern is transferred to the front nitride layer 36 using anRIE etch. A layer of LPCVD polysilicon 40 is deposited on the front, anda similar layer 42 is applied to the back of the wafer; both layers are0.5 microns thick.

[0024]FIG. 9 illustrates the wafer at the conclusion of step 36. Thefront side of the wafer is patterned with polysilicon structures 44 andthen RIE etched to transfer the pattern to the polysilicon layer 40. Thephotoresist is left on, the wafer is flipped and another layer ofpolysilicon (not shown) is deposited on the backside and RIE etched. Thewafer is flipped again and the front side resist is removed, which isacting as a protective layer for the front side when flipped. A layer ofPECVD polysilicon glass (PSG) 46 is added to the front of the waver anddensified to 2 microns.

[0025]FIG. 10 illustrates the wafer after step 46. Holes 48 arepatterned in the PSG layer 46 and an RIE etch is done to transfer thepattern to the PSG layer using the polysilicon layer 40 as an etch stop.The photoresist is removed and a front layer 50 and back layer 52 ofLPCVD polysilicon 2 micros thick are deposited, followed by a deposit of0.2 microns of PECVD polysilicon glass (PSG) (not shown), and the waferis annealed at 1,000° C. for one hour to dope the polysilicon layers 50and 52 and reduce stress.

[0026]FIG. 11 illustrates the wafer at the conclusion of step 52. ThisPSG layer 46 is patterned with polysilicon structures 56, and an RIEetch is performed to transfer the pattern to a PSG hard mask, followedby an RIE etch to transfer the pattern to the polysilicon layer 50. Theresist is left on and the wafer is flipped and RIE etched to remove thebackside polysilicon 52, using the front side resist and hard mask toprotect the front. The wafer is flipped back over when done, thephotoresist is removed, and the hard mask is removed with an RIE etch,which thins any exposed oxide by about 0.3 microns. A layer of PECVDpolysilicon glass (PSG2) 54, is deposited and densified to 0.75 microns.

[0027]FIG. 12 illustrates the wafer at the conclusion of step 55. Holes58 are patterned in the PSG2 layer 54 and an RIE etch is performed totransfer the pattern to the PSG, using the polysilicon layer as an etchstop. The photoresist is then removed.

[0028]FIG. 13 illustrates the wafer at the conclusion of step 68. Thethermal oxide layer 20 is patterned with polysilicon structures and anRIE etch is performed to transfer the pattern to the PSG hard mask. AnRIE etch is performed to transfer the pattern to the polysilicon 54. Thewafer is flipped and an RIE etch is performed to remove the backsidepolysilicon, using the front side resist and hard mask to protect thefront. The resist is removed, and the hard mask is removed with an RIEetch.

[0029]FIG. 14 illustrates the wafer at the conclusion of step 70. Areason the front side where the POX 32 should be removed are patterned. Thislayer should only be used in areas where there is no polysilicon ormetal, since those would act as etch stops for the subsequent etches. Awet etch is performed to remove the thermal oxide layer 20, exposingselected areas of the SCS layer 12. Designers must be careful that therenearby structures aren't damaged by a hydrofluoric acid (HF) etch.Polysilicon layers previously put on the SCS layer can be etched awaywithout etching any of the SCS layer because the SCS layer 12 itselfcreates an etch stop.

[0030] Exposure of selected areas of the SCS layer at this point in theprocess allows mechanical, electrical and optical strcutures to be builtdirectly onto the selected areas after other important structural (i.e.,non-sacrificial) features have been built onto the SCS. Thesemechanical, electrical and optical structures are thus better able totake advantage of the SCS layer's useful properties. In the embodimentshown, a metal coating 60 is applied directly onto the grating 28previously etched into the SCS layer 12 (see FIG. 15). Application ofthe metal coating 60 turns the grating 28 into a reflecting grating.Similarly, metal elements can be put on the SCS layer to conductelectrical current, insulating elements can be built on the SCS usingnitride or oxide layers, or elements comprising both conducting andinsulating parts can be built onto the SCS layer.

[0031]FIG. 15 illustrates the wafer at the conclusion of step 76. Aphotoresist is patterned for lift-off metal and 0.5 microns of metal 60are deposited on the grating 28 on the front side of the SCS layer 12.The resist is lifted off, removing metals in those areas. A pattern isapplied with areas where metal should be removed, and 200 Å of chromium(Cr) are deposited on the front side of the grating 28, followed by 300Å of gold (Au). In this case, the gold increases the reflectivity of thegrating, and because of how it is deposited it also smoothes the edgesof the grating. Other metals having required reflectivity may also beused on the grating 28; examples include aluminum (Al) and platinum(Pt). The resist and the metal coating resist are then removed.

[0032]FIG. 16 illustrates the wafer at the conclusion of step 84. Thebackside nitride/oxide layer 38 is patterned with holes sized so thatKOH will etch the desired depth. Uncertainty in wafer thickness willaffect the size of the holes created at the other side of the wafer. Thepattern is transferred to the nitride layer 38 with an RIE etch, and thesame pattern is also transferred to the oxide layer 18 with an RIE etch.A through-wafer KOH etch is performed while protecting the front sidewith a deposited layer. If a coating is used it should be left on forthe next step which involves removing the backside nitride/oxide using anitride RIE etch and then an oxide RIE etch, which clears off exposedburied SCS. The protective layer possibly present from the last stepwill protect the front side. Backside etching of the wafer 10 ispossible because in this process because of the use of differentmaterials for the substrate layer 14 (which is made of polysilicon) andthe device layer 12 (made of single crystal silicon). This enables thesubstrate to be etched away without etching away the backside of thedevice layer, and allows both sides of the device layer to be used tomake various components mechanical and optical components such as thetwo-sided mirror shown.

[0033] To make the two-sided grating 204, a blanket deposit of 0.1microns of metal 62 is deposited on the backside of the wafer tometalize the backside of the mirror. The metal is sputtered onto thebackside of the wafer; suitable metals for metalization of the backsideinclude all the metals used on the front layer 60. If the componentwhose backside is to be metalized has holes which extend through thedevice layer, the backside metal must be deposited carefully to ensurethat the metal does not flow through the holes and ruin the quality ofthe front surface of the device. This is particularly important withoptical components, where the front surface must have near-perfectoptical qualities and no flow-through from back to front can betolerated. An effective way of addressing this problem of metal flowingthrough to the front surface is to tilt the wafer while the metal issputtered onto the backside; this prevents flow-through of the metal.Any exposed holes in the SCS layer 12 must be kept small (approximately2 microns) to prevent sputtered metal from traveling all the way throughthe wafer. The same technique can be used when sputtering metal on thefront side of the wafer if a two-sided optical component is needed.

[0034] Metalization of the backside of a component such as the grating204 has several advantages. Among other things, the backsidemetalization helps with the release of the component once it's finished.When used on a one-sided optical device such as a mirror, backsidemetalization reduces transmission of light through the mirror. Backsidemetalization also helps ensure that any residual stresses in the mirrorare balanced, so that the grating 204 will not become distorted.Finally, backside metalization allows two-sided optical components to bemade.

[0035]FIGS. 17 and 18 illustrate the wafer at the conclusion of theprocess after the grating 204 built into the wafer has been released.The release may be performed by any of various methods includingstandard MUMPS methods which include (1) stripping the photoresist bysoaking in acetone for 20 to 30 minutes with mild agitation, (2) etchingin 49% straight HF for 2 ½ to 3 minutes and rinsing in de-ionized waterfor 10 minutes, or (3) rinse in IPA for 5 minutes and bake the chip at100-110° C. for 10 to 15 minutes.

[0036] Since the fabrication technology utilized to producemicrooptoelectromechanical (MOEMS) components can lead to manufacturingbarriers in the thin film properties associated with the process, thepresent invention includes an enabling fabrication process formicrooptoelectromechanical systems that overcomes the barriers in theoptomechanical properties of thin film structures. The key innovation toovercoming these thin film properties is to utilize silicon on insulator(SOI) wafers as the starting substrate in a surface micromachiningprocess (see FIG. 1). SOI is a generic term that refers to a structurein which a silicon layer is supported by a dielectric material. In thisembodiment, a silicon device layer, bonded to a conventional siliconhandle wafer, has a SiO₂ thin-film layer at the interface. This allowscritical optical and electronic components to be fabricated in a singlecrystal silicon device layer, which can be released from the handlewafer by etching the oxide at the interface between the device layer andthe substrate.

[0037] The oxide layer at the interface can also be utilized as abackside etch stop layer for releasing optical components, such as amirror, that cannot include etch holes. The device layer has a userspecified thickness that is appropriate for the given application, andhas excellent and reproducible electrical and thin film properties. Boththe back and front side of the device layer would be polished, and thusoptical elements fabricated in this layer do not require additionalpost-processing chemical-mechanical polish (CMP) techniques to obtain anoptical quality surface finish. Since the device layer is single crystalsilicon, it has no intrinsic stress or stress gradients in the absenceof thin film coatings. Since it can be made thicker than conventionalchemical vapor deposition (CVD) deposited thin films, optical componentsfabricated in this layer have minimal distortions after thin filmdepositions such as aluminum to increase surface reflectivity, ordielectric thin films to decrease surface reflectivity. The additionalthickness is also important to minimize distortions for dynamicallyactuated optical elements.

[0038] As those skilled in the art will appreciate, other variousmodifications, extensions, and changes to the foregoing disclosedembodiments of the present invention are contemplated to be within thescope and spirit of the invention as defined in the following claims.

1. A micromechanical or microoptomechanical structure produced by aprocess comprising: defining the structure in a single-crystal siliconlayer separated by an insulator layer from a substrate layer;selectively etching the single crystal silicon layer; depositing andetching a polysilicon layer on the insulator layer, with remainingpolysilcon forming mechanical elements of the structure; metalizing abackside of the structure; and releasing the formed structure.
 2. Themicrostructure of claim 1 wherein selectively etching the single crystalsilicon further comprises the step photolithographically patterning anddry etching the single crystal silicon layer.
 3. The structure of claim1 wherein the insulator layer is an oxide layer.
 4. The structure ofclaim 1 wherein metalizing the backside of the structure comprises:etching the substrate layer and insulator away from a backside of thewafer until a backside of the single crystal silicon layer of thestructure is exposed; and depositing a coating of metal on the exposedbackside of the single crystal silicon layer of the structure.
 5. Thestructure of claim 4 wherein the metal is selected from the groupconsisting of gold, aluminum, chromium and platinum.
 6. A process formaking a micromechanical or microoptomechanical structure in a wafercomprising a single crystal silicon layer bonded to a substrate layer byan insulator layer, the process comprising: defining the structure inthe single-crystal silicon layer; selectively etching the single crystalsilicon layer; photolithographically patterning and etching theselectively etched single crystal silicon layer and the oxide layer,depositing and patterning a polysilicon layer on the insulator layer;metalizing a backside of the structure; and releasing the formedstructure.
 7. The process of claim 6 wherein selectively etching thesingle crystal silicon further comprises the step photolithographicallypatterning and dry etching the single crystal silicon layer.
 8. Theprocess of claim 6 wherein the insulator layer is an oxide layer.
 9. Theprocess of claim 6 wherein metalizing the backside of the structurecomprises: etching the substrate layer and insulator away from abackside of the wafer until a backside of the single crystal siliconlayer of the structure is exposed; and depositing a coating of metal onthe exposed backside of the single crystal silicon layer of thestructure.
 10. The process of claim 9 wherein the metal is selected fromthe group consisting of gold, aluminum, chromium and platinum.
 11. Theprocess of claim 6 further comprising: depositing a PSG layer on thepolysilicon layer; patterning the PSG layer and polysilicon layer;depositing a protective oxide layer prior to releasing the formedmicrooptical structure.